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features ? high performance, low power avr ? 8-bit microcontroller ? advanced risc architecture ? 131 powerful instructions - most single clock cycle execution ? 32 x 8 general purpose working registers ? fully static operation ? up to 8 mips throughput at 8 mhz ? high endurance non-volatile memory segments ? 16k/32k bytes of in-system self-programmable flash (atmega16hvb/32hvb) ? 512/1k bytes eeprom ? 1k/2k bytes internal sram ? write/erase cycles 10, 000 flash/100,000 eeprom ? data retention: 20 years at 85c/100 years at 25c (1) ? optional boot code section with independent lock bits in-system programming by on-chip boot program true read-while-write operation ? programming lock for software security ? battery management features ? two, three or four cells in series ? high-current protection (charge and discharge) ? over-current protection (charge and discharge) ? short-circuit protection (discharge) ? high voltage outputs to drive n-channel charge/discharge fets ? optional deep under voltage recovery mo de - allowing 0-volt charging without external precharge fet ? optional high voltage open drain ouput - allowing 0-volt charging with external precharge fet ? integrated cell balancing fets ? peripheral features ? two configurable 8- or 16-bit timers with separate prescaler, optional input capture (ic), compare mode and ctc ? spi - serial peripheral interface ? 12-bit voltage adc, six external and one internal adc input ? high resolution coulomb counter adc for current measurements ? twi serial interface supporting smbus implementation ? programmable watchdog timer ? special microcontroller features ? debugwire on-chip debug system ? in-system programmable via spi ports ?power-on reset ? on-chip voltage regulator with short-circuit monitoring interface ? external and internal interrupt sources ? sleep modes: idle, adc noise redu ction, power-save, and power-off ? additional secure authentication features available only under nda ? packages ? 44-pin tssop ? operating voltage: 4 - 25v ? maximum withstand voltage (high-voltage pins): 35v ? temperature range: -40c to 85c ? speed grade: 1-8 mhz note: 1. see ?data retention? on page 8 for details. 8-bit microcontroller with 16k/32k bytes in-system programmable flash atmega16hvb atmega32hvb preliminary summary 8042b?avr?06/10
2 8042b?avr?06/10 atmega16hvb/32hvb 1. pin configurations 1.1 tssop figure 1-1. tssop - pinout atmega16hvb/32hvb 1.2 pin descriptions 1.2.1 vfet high voltage supply pin. this pin is used as suppl y for the internal voltage regulator, described in ?voltage regulator? on page 130 . 1.2.2 vcc digital supply voltage. no rmally connected to vreg. 1.2.3 vreg output from the internal voltage regulator. used for external decoupling to ensure stable regu- lator operation. for details, see ?voltage regulator? on page 130 . 1 44 3 pi ppi nv pv1 pv2 pv3 pv4 pvt vcc gnd pc5 pc4(scl) pc3(int3/sda) pc2(int2) pc1(int1) pc0(int0/extprot) pb7(miso/pcint11) nc pb6(mosi/pcint10) pb5(sck/pcint9) pb4(ss/pcint8) pb3(pcint7) 2 4 5 6 7 8 9 10 11 12 1 3 14 15 16 17 1 8 19 20 21 22 4 3 42 41 40 3 9 38 3 7 3 6 3 5 3 4 33 3 2 3 1 3 0 29 2 8 27 26 25 24 2 3 ni nni vrefgnd vref gnd vreg pa0(adc0/sgnd/pcint0) pa1(adc1/sgnd/pcint1) pa2(pcint2/t0) pa3(pcint3/t1) vclmp10 vfet batt vcc gnd od nc oc reset/dw pb0(pcint4/icp00) pb1(pcint5/ckout) pb2(pcint6)
3 8042b?avr?06/10 atmega16hvb/32hvb 1.2.4 vref internal voltage reference for external decoupling. for details, see ?voltage reference and temperature sensor? on page 122 . 1.2.5 vrefgnd ground for decoupling of internal voltage reference. for details, see ?voltage reference and temperature sensor? on page 122 . do not connect to gnd or sgnd on pcb. 1.2.6 gnd ground 1.2.7 port a (pa3..pa0) port a serves as a low-voltage 4-bit bi-directional i/o port with internal pull-up resistors (selected for each bit). as inputs, port a pins that are externally pulled low will source current if the pull-up resistors are activated. the port a pins are tri-stated when a reset condition becomes active, even if the clock is not running. port a also serves the functions of various special features of the atmega16hvb/32hvb as listed in ?alternate functions of port a? on page 74 . 1.2.8 port b (pb7..pb0) port b is a low-voltage 8-bit bi-directional i/o port with internal pull-up resistors (selected for each bit). as inputs, port b pins that are exter nally pulled low will source current if the pull-up resistors are activated. the port b pins are tri-stated when a reset condition becomes active, even if the clock is not running. port b also serves the functions of various special features of the atmega16hvb/32hvb as listed in ?alternate functions of port b? on page 75 . 1.2.9 port c (pc5) port c (pc5) is a high voltage open drain output port. port c serves the functions of various special features of the at mega16hvb/32hvb as listed in ?alternate functions of port c? on page 65 . 1.2.10 port c (pc4..pc0) port c is a 5-bit high voltage open drain bi-direc tional i/o port. port c serves the functions of various special features of the atmega16hvb/32hvb as listed in ?alternate functions of port c? on page 65 . 1.2.11 oc/od high voltage output to drive charge/discharge. for details, see ?fet driver? on page 145 . 1.2.12 pi/ni filtered positive/negative input from external cu rrent sense resistor, used to by the coulomb counter adc to measure charge/discharge currents flowing in the battery pack. for details, see ?coulomb counter - dedicated fuel gauging sigma-delta adc? on page 108 .
4 8042b?avr?06/10 atmega16hvb/32hvb 1.2.13 ppi/nni unfiltered positive/negative input from external current sense resistor, used by the battery pro- tection circuit, for over-current and short-circuit detection. for details, see ?battery protection? on page 133 . 1.2.14 nv/pv1/pv2/pv3/pv4 nv, pv1, pv2, pv3, and pv4 are the inputs for battery cells 1, 2, 3 and 4, used by the voltage adc to measure each cell voltage. for details, see ?voltage adc ? 7-channel general purpose 12-bit sigma-delta adc? on page 116 . 1.2.15 pvt defines the source voltage level for the charge fet driver. for details, see ?fet driver? on page 145 . 1.2.16 batt input for detecting when a charger is connected. defines the source voltage level for the dis- charge fet driver. for details, see ?fet driver? on page 145 . 1.2.17 reset /dw reset input. a low level on this pin for longer than the minimum pulse length will generate a reset, even if the clock is not running. the minimum pulse length is given in table 11 on page 38. shorter pulses are not guaranteed to generate a reset. this pin is also used as debugwire communication pin.
5 8042b?avr?06/10 atmega16hvb/32hvb 2. overview the atmega16hvb/32hvb is a monitoring and protection circuit for 3 and 4-cell li-ion applica- tions with focus on highest safety including safe authentication, low co st and high utilization of the cell energy. the device contains secure authentication features as well as autonomous bat- tery protection during charging and discharging. the external protection input can be used to implement other battery protection mechanisms using external components, e.g. protection against chargers with too high charge voltage can be easily implemented with a few low cost passive components. the feature set makes the atmega16hvb/32hvb a key component in any system focusing on high secu rity, battery protection, high system utilization and low cost. figure 2-1. block diagram atmega16hvb/32hvb provides the necessary redundancy on-chip to make sure that the bat- tery is protected in critical failure modes. the chip is specifically designed to provide safety for the battery cells in case of pin shorting, loss of power (either caused by battery pack short or vcc short), illegal charger conne ction or software runaway. this make s atmega16hvb/32hvb the ideal 1-chip solution for applications with focus on high safety. the atmega16hvb/32hvb features an integrated voltage regulator that operates at a wide range of input voltages, 4 - 25 volts. this voltage is regulated to a constant supply voltage of nominally 3.3 volts for the integr ated logic and analog functions. the regulator capabilities, com- porta (4) sram flash cpu eeprom pv2 nv oc fet control voltage adc voltage reference coulomb counter adc gnd vcc reset/dw power supervision por & reset watchdog oscillator watchdog timer oscillator circuits / clock generation vref vrefgnd pi ni pa3..0 pa1..0 8/16-bit t/c1 8/16-bit t/c0 portb (8) pb7..0 spi voltage regulator charger detect vfet vreg batt pv1 data b u s v p tat current protection security module portc (6) pc5..0 voltage regulator monitor interface pb0 oscillator sampling interface program logic debugwire cell balancing pv3 pv4 twi ppi nni od porta (4) sram flash cpu eeprom pv2 nv oc fet control voltage adc voltage reference coulomb counter adc gnd vcc reset/dw power supervision por & reset watchdog oscillator watchdog timer oscillator circuits / clock generation vref vrefgnd pi ni pa3..0 pa1..0 8/16-bit t/c1 8/16-bit t/c0 portb (8) pb7..0 spi voltage regulator charger detect vfet vreg batt pv1 data b u s v p tat current protection security module portc (6) pc5..0 voltage regulator monitor interface pb0 oscillator sampling interface program logic debugwire cell balancing pv3 pv4 twi ppi nni od
6 8042b?avr?06/10 atmega16hvb/32hvb bined with an extremely low power consumption in the power saving modes, greatly enhances the cell energy utilization compared to existing solutions. the chip utilizes atmel's patented deep under-voltage recovery (duvr) mode that supports pre-charging of deeply discharged battery cells without using a separate pre-charge fet. duvr mode cannot be used in 2-cell applications. optionally, pre-charge fets are supported for inte- gration into many existing battery charging schemes. the battery protection monitors the charge and dischar ge current to detect illegal conditions and protect the battery from these when required. a 12-bit voltage adc allows software to monitor each cell voltage individually with high accuracy. the adc also provides one internal input chan- nel to measure on-chip temperature and two i nput channels intended for external thermistors. an 18-bit adc optimized for coulomb counting accumulates charge and discharge currents and reports accumulated current with high resoluti on and accuracy. it can also be used to provide instantaneous current measurements with 13 bit resolution. integrated cell balancing fets allow cell balancing algorithms to be implemented in software. the mcu provides the following features: 16k/32k bytes of in-system programmable flash with read-while-write capabilities, 512/1k bytes eeprom, 1k/2k by tes sram. 32 general purpose working registers, 12 general purpose i/o lines, 5 general purpose high voltage open drain i/o lines, one general purpose super high voltage open drain output, debugwire for on-chip debugging and spi for in-system programming, a sm-bus comp liant twi module, two flexible timer/counters with input capture and compare modes. internal and external interrupts, a 12-bit sigma delta adc for voltage and temperature measure- ments, a high resolution sigma delta adc for coulomb counting and instantaneous current measurements, integrated cell balancing fets, additional secure authentication features, an autonomous battery protection m odule, a programmable watchdog timer with internal oscilla- tor, and software selectable power saving modes. the avr core combines a rich instruction set with 32 general purpose working registers. all the 32 registers are directly connected to the arithmetic logic unit (alu), allowing two independent registers to be accessed in one single instruction executed in one clock cycle. the resulting architecture is more code efficient while achiev ing throughputs up to ten times faster than con- ventional cisc microcontrollers. the device is manufactured using atmel?s high voltage high density non-volatile memory tech- nology. the on-chip isp flash allows the program memory to be reprogrammed in-system, through an spi serial interface, by a conventiona l non-volatile memory programmer or by an on- chip boot program running on the avr core. the boot program can use any interface to down- load the application program in the application flash memory. software in the boot flash section will continue to run while the applicati on flash section is updated, providing true read- while-write operation. by combining an 8-bit risc cpu with in-system self-programmable- flash and highly accurate analog front-end in a monolithic chip. the atmel atmega16hvb/32hvb is a powerful microcontroller that provides a highly flexible and cost effective solution. it is part of the avr battery management family that provides secure authentication, highly accurate monitoring and autonomous protection for lithium-ion battery cells. the atmega16hvb/32hvb avr is supported with a full suite of program and system develop- ment tools including: c compilers, macro assemblers, program debugger/simulators, and on- chip debugger.
7 8042b?avr?06/10 atmega16hvb/32hvb 2.1 comparison between atmega16hvb and atmega32hvb the atmega16hvb and atmega32hvb differ only in memory size for flash, eeprom and internal sram. table 2-1 summarizes the different conf iguration for the two devices. table 2-1. configuration summary device flash eeprom sram atmega16hvb 16k 512 1k atmega32hvb 32k 1k 2k
8 8042b?avr?06/10 atmega16hvb/32hvb 3. disclaimer all min, typ and max values contained in this datasheet are preliminary estimates based on sim- ulations and characterization of other avr microcontrollers manufactured on the same process technology. final values will be availa ble after the device is characterized. 4. resources a comprehensive set of development tools, app lication notes and datasheets are available for download on http:// www.atmel.com/avr.n1 note: 1. 5. about code examples this documentation contains simple code examples that briefly show how to use various parts of the device. these code examples assume that the part specific header file is included before compilation. be aware that not all c compiler vendors include bit definitions in the header files and interrupt handling in c is compiler dependent. please confirm with the c compiler documen- tation for more details. for i/o registers located in extended i/o map, ?in?, ?out?, ?sbis?, ?sbic?, ?cbi?, and ?sbi? instructions must be replaced with instructio ns that allow access to extended i/o. typically ?lds? and ?sts? combined with ? sbrs?, ?sbrc?, ?sbr?, and ?cbr?. 6. data retention reliability qualification results show that the pr ojected data retention failure rate is much less than 1 ppm over 20 years at 85c or 100 years at 25c.
9 8042b?avr?06/10 atmega16hvb/32hvb 7. register summary address name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 page (0xff) reserved ? ? ? ? ? ? ? ? (0xfe) bpplr ? ? ? ? ? ? bpple bppl 140 (0xfd) bpcr ? ? epid scd docd cocd dhcd chcd 141 (0xfc) bphctr ? ? hcpt[5:0] 143 (0xfb) bpoctr ? ? ocpt[5:0] 142 (0xfa) bpsctr ? scpt[6:0] 142 (0xf9) bpchcd chcdl[7:0] 145 (0xf8) bpdhcd dhcdl[7:0] 145 (0xf7) bpcocd cocdl[7:0] 145 (0xf6) bpdocd docdl[7:0] 144 (0xf5) bpscd scdl[7:0] 144 (0xf4) reserved ? ? ? ? ? ? ? ? (0xf3) bpifr ? ? ? scif docif cocif dhcif chcif 147 (0xf2) bpimsk ? ? ? scie docie cocie dhcie chcie 146 (0xf1) cbcr ? ? ? ? cbe4 cbe3 cbe2 cbe1 155 (0xf0) fcsr ? ? ? ? duvrd cps dfe cfe 153 (0xef) reserved ? ? ? ? ? ? ? ? (0xee) reserved ? ? ? ? ? ? ? ? (0xed) reserved ? ? ? ? ? ? ? ? (0xec) reserved ? ? ? ? ? ? ? ? (0xeb) reserved ? ? ? ? ? ? ? ? (0xea) cadrdc cadrdc[7:0] 115 (0xe9) cadrcc cadrcc[7:0] 115 (0xe8) cadcsrc - - - - - - - cadvse 114 (0xe7) cadcsrb ? cadacie cadrcie cadicie ? cadacif cadrcif cadicif 112 (0xe6) cadcsra caden cadpol cadub cadas[1:0] cadsi[1:0] cadse 111 (0xe5) cadich cadic[15:8] 114 (0xe4) cadicl cadic[7:0] 114 (0xe3) cadac3 cadac[31:24] 114 (0xe2) cadac2 cadac[23:16] 114 (0xe1) cadac1 cadac[15:8] 114 (0xe0) cadac0 cadac[7:0] 114 (0xdf) reserved ? ? ? ? ? ? ? ? (0xde) reserved ? ? ? ? ? ? ? ? (0xdd) reserved ? ? ? ? ? ? ? ? (0xdc) reserved ? ? ? ? ? ? ? ? (0xdb) reserved ? ? ? ? ? ? ? ? (0xda) reserved ? ? ? ? ? ? ? ? (0xd9) reserved ? ? ? ? ? ? ? ? (0xd8) reserved ? ? ? ? ? ? ? ? (0xd7) reserved ? ? ? ? ? ? ? ? (0xd6) reserved ? ? ? ? ? ? ? ? (0xd5) reserved ? ? ? ? ? ? ? ? (0xd4) chgdcsr ? ? ? battpvl chgdisc1 chgdi sc1 chgdif chgdie 131 (0xd3) reserved ? ? ? ? ? ? ? ? (0xd2) bgcsr ? ?bgdbgscde ? ? bgscdif bgscdie 127 (0xd1) bgcrr bgcr[7:0] 126 (0xd0) bgccr ? ? bgcc[5:0] 9 (0xcf) reserved ? ? ? ? ? ? ? ? (0xce) reserved ? ? ? ? ? ? ? ? (0xcd) reserved ? ? ? ? ? ? ? ? (0xcc) reserved ? ? ? ? ? ? ? ? (0xcb) reserved ? ? ? ? ? ? ? ? (0xca) reserved ? ? ? ? ? ? ? ? (0xc9) reserved ? ? ? ? ? ? ? ? (0xc8) rocr rocs ? ?rocd ? ? rocwif rocwie 134 (0xc7) reserved ? ? ? ? ? ? ? ? (0xc6) reserved ? ? ? ? ? ? ? ? (0xc5) reserved ? ? ? ? ? ? ? ? (0xc4) reserved ? ? ? ? ? ? ? ? (0xc3) reserved ? ? ? ? ? ? ? ? (0xc2) reserved ? ? ? ? ? ? ? ? (0xc1) reserved ? ? ? ? ? ? ? ? (0xc0) reserved ? ? ? ? ? ? ? ?
10 8042b?avr?06/10 atmega16hvb/32hvb (0xbf) reserved ? ? ? ? ? ? ? ? (0xbe) twbcsr twbcif twbcie ? ? ? twbdt1 twbdt0 twbcip 187 (0xbd) twamr twam[6:0] ?187 (0xbc) twcr twint twea twsta twsto twwc twen ?twie 184 (0xbb) twdr 2?wire serial interface data register 186 (0xba) twar twa[6:0] twgce 186 (0xb9) twsr tws[7:3] ?twps1twps0 185 (0xb8) twbr 2?wire serial interface bit rate register 184 (0xb7) reserved ? ? ? ? ? ? ? (0xb6) reserved ? ? ? ? ? ? ? ? (0xb5) reserved ? ? ? ? ? ? ? ? (0xb4) reserved ? ? ? ? ? ? ? ? (0xb3) reserved ? ? ? ? ? ? ? ? (0xb2) reserved ? ? ? ? ? ? ? ? (0xb1) reserved ? ? ? ? ? ? ? ? (0xb0) reserved ? ? ? ? ? ? ? ? (0xaf) reserved ? ? ? ? ? ? ? ? (0xae) reserved ? ? ? ? ? ? ? ? (0xad) reserved ? ? ? ? ? ? ? ? (0xac) reserved ? ? ? ? ? ? ? ? (0xab) reserved ? ? ? ? ? ? ? ? (0xaa) reserved ? ? ? ? ? ? ? ? (0xa9) reserved ? ? ? ? ? ? ? ? (0xa8) reserved ? ? ? ? ? ? ? ? (0xa7) reserved ? ? ? ? ? ? ? ? (0xa6) reserved ? ? ? ? ? ? ? ? (0xa5) reserved ? ? ? ? ? ? ? ? (0xa4) reserved ? ? ? ? ? ? ? ? (0xa3) reserved ? ? ? ? ? ? ? ? (0xa2) reserved ? ? ? ? ? ? ? ? (0xa1) reserved ? ? ? ? ? ? ? ? (0xa0) reserved ? ? ? ? ? ? ? ? (0x9f) reserved ? ? ? ? ? ? ? ? (0x9e) reserved ? ? ? ? ? ? ? ? (0x9d) reserved ? ? ? ? ? ? ? ? (0x9c) reserved ? ? ? ? ? ? ? ? (0x9b) reserved ? ? ? ? ? ? ? ? (0x9a) reserved ? ? ? ? ? ? ? ? (0x99) reserved ? ? ? ? ? ? ? ? (0x98) reserved ? ? ? ? ? ? ? ? (0x97) reserved ? ? ? ? ? ? ? ? (0x96) reserved ? ? ? ? ? ? ? ? (0x95) reserved ? ? ? ? ? ? ? ? (0x94) reserved ? ? ? ? ? ? ? ? (0x93) reserved ? ? ? ? ? ? ? ? (0x92) reserved ? ? ? ? ? ? ? ? (0x91) reserved ? ? ? ? ? ? ? ? (0x90) reserved ? ? ? ? ? ? ? ? (0x8f) reserved ? ? ? ? ? ? ? ? (0x8e) reserved ? ? ? ? ? ? ? ? (0x8d) reserved ? ? ? ? ? ? ? ? (0x8c) reserved ? ? ? ? ? ? ? ? (0x8b) reserved ? ? ? ? ? ? ? ? (0x8a) reserved ? ? ? ? ? ? ? ? (0x89) ocr1b timer/counter1 ? output compare register b 95 (0x88) ocr1a timer/counter1 ? output compare register a 95 (0x87) reserved ? ? ? ? ? ? ? ? (0x86) reserved ? ? ? ? ? ? ? ? (0x85) tcnt1h timer/counter1 (8 bit) high byte 95 (0x84) tcnt1l timer/counter1 (8 bit) low byte 95 (0x83) reserved ? ? ? ? ? ? ? ? (0x82) reserved ? ? ? ? ? ? ? ? (0x81) tccr1b ? ? ? ? ? cs12 cs11 cs10 81 (0x80) tccr1a tcw1 icen1 icnc1 ices1 ics1 ? ?wgm10 94 (0x7f) reserved ? ? ? ? ? ? ? ? (0x7e) didr0 ? ? ? ? ? ? pa1did pa0did 122 address name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 page
11 8042b?avr?06/10 atmega16hvb/32hvb (0x7d) reserved ? ? ? ? ? ? ? ? (0x7c) vadmux ? ? ? ? vadmux[3:0] 120 (0x7b) reserved ? ? ? ? ? ? ? ? (0x7a) vadcsr ? ? ? ? vaden vadsc vadccif vadccie 120 (0x79) vadch ? ? ? ? vadc data register high byte 121 (0x78) vadcl vadc data register low byte 121 (0x77) reserved ? ? ? ? ? ? ? ? (0x76) reserved ? ? ? ? ? ? ? ? (0x75) reserved ? ? ? ? ? ? ? ? (0x74) reserved ? ? ? ? ? ? ? ? (0x73) reserved ? ? ? ? ? ? ? ? (0x72) reserved ? ? ? ? ? ? ? ? (0x71) reserved ? ? ? ? ? ? ? ? (0x70) reserved ? ? ? ? ? ? ? ? (0x6f) timsk1 ? ? ? ? icie1 ocie1b ocie1a toie1 96 (0x6e) timsk0 ? ? ? ? icie0 ocie0b ocie0a toie0 96 (0x6d) reserved ? ? ? ? ? ? ? ? (0x6c) pcmsk1 pcint[15:8] 60 (0x6b) pcmsk0 ? ? ? ? pcint[3:0] 61 (0x6a) reserved ? ? ? ? ? ? ? ? (0x69) eicra isc31 isc30 isc21 isc20 isc11 isc10 isc01 isc00 58 (0x68) pcicr ? ? ? ? ? ?pcie1pcie0 60 (0x67) reserved ? ? ? ? ? ? ? ? (0x66) fosccal fast oscillator calibration register 32 (0x65) reserved ? ? ? ? ? ? ? ? (0x64) prr0 ? prtwi prvrm ? prspi prtim1 prtim0 prvadc 40 (0x63) reserved ? ? ? ? ? ? ? ? (0x62) reserved ? ? ? ? ? ? ? ? (0x61) clkpr clkpce ? ? ? ? ? clkps1 clkps0 32 (0x60) wdtcsr wdif wdie wdp3 wdce wde wdp2 wdp1 wdp0 49 0x3f (0x5f) sreg i t h s v n z c 10 0x3e (0x5e) sph sp15 sp14 sp13 sp12 sp11 sp10 sp9 sp8 13 0x3d (0x5d) spl sp7 sp6 sp5 sp4 sp3 sp2 sp1 sp0 13 0x3c (0x5c) reserved ? ? ? ? ? ? ? ? 0x3b (0x5b) reserved ? ? ? ? ? ? ? ? 0x3a (0x5a) reserved ? ? ? ? ? ? ? ? 0x39 (0x59) reserved ? ? ? ? ? ? ? ? 0x38 (0x58) reserved ? ? ? ? ? ? ? ? 0x37 (0x57) spmcsr spmie rwwsb sigrd ctpb rflb pgwrt pgers spmen 206 0x36 (0x56) reserved ? ? ? ? ? ? ? ? 0x35 (0x55) mcucr ? ?ckoepud ? ? ivsel ivce 78/32 0x34 (0x54) mcusr ? ? ? ocdrf wdrf bodrf extrf porf 49 0x33 (0x53) smcr ? ? ? ? sm[2:0] se 39 0x32 (0x52) reserved ? ? ? ? ? ? ? ? 0x31 (0x51) dwdr debugwire data register 190 0x30 (0x50) reserved ? ? ? ? ? ? ? ? 0x2f (0x4f) reserved ? ? ? ? ? ? ? ? 0x2e (0x4e) spdr spi data register 107 0x2d (0x4d) spsr spif wcol ? ? ? ? ?spi2x 106 0x2c (0x4c) spcr spie spe dord mstr cpol cpha spr1 spr0 105 0x2b (0x4b) gpior2 general purpose i/o register 2 24 0x2a (0x4a) gpior1 general purpose i/o register 1 24 0x29 (0x49) ocr0b timer/counter0 output compare register b 95 0x28 (0x48) ocr0a timer/counter0 output compare register a 95 0x27 (0x47) tcnt0h timer/counter0 (8 bit) high byte 95 0x26 (0x46) tcnt0l timer/counter0 (8 bit) low byte 95 0x25 (0x45) tccr0b ? ? ? ? ? cs02 cs01 cs00 81 0x24 (0x44) tccr0a tcw0 icen0 icnc0 ices0 ics0 ? ?wgm00 94 0x23 (0x43) gtccr tsm ? ? ? ? ? ? psrsync 0x22 (0x42) eearh ? ? ? ? ? ? eeprom high byte 20 0x21 (0x41) eearl eeprom address register low byte 20 0x20 (0x40) eedr eeprom data register 20 0x1f (0x3f) eecr ? ? eepm1 eepm0 eerie eempe eepe eere 21 0x1e (0x3e) gpior0 general purpose i/o register 0 24 0x1d (0x3d) eimsk ? ? ? ? int3 int2 int1 int0 59 0x1c (0x3c) eifr ? ? ? ? intf3 intf2 intf1 intf0 59 address name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 page
12 8042b?avr?06/10 atmega16hvb/32hvb notes: 1. for compatibility with future devices, reserved bits s hould be written to zero if accessed. reserved i/o memory address es should never be written. 2. i/o registers within the address range $00 - $1f are directly bit-accessible using th e sbi and cbi instructions. in these reg - isters, the value of single bits can be checked by using the sbis and sbic instructions. 3. some of the status flags are cleared by writing a logical o ne to them. note that the cbi and sbi instructions will operate on all bits in the i/o register, writing a one back into any flag r ead as set, thus clearing the fl ag. the cbi and sbi instruction s work with registers 0x00 to 0x1f only. 4. when using the i/o specific commands in and out, the i/o addresses $00 - $3f must be used. when addressing i/o regis- ters as data space using ld and st instructions, $20 mu st be added to these addresses. the atmega16hvb/32hvb is a complex microcontroller with more peripheral units than can be supported within the 64 location reserved in opcode for the in and out instructions. for the ext ended i/o space from $60 - $ff in sram, only the st/sts/std and ld/lds/ldd instructions can be used. 0x1b (0x3b) pcifr ? ? ? ? ? ?pcif1pcif0 60 0x1a (0x3a) reserved ? ? ? ? ? ? ? ? 0x19 (0x39) reserved ? ? ? ? ? ? ? ? 0x18 (0x38) reserved ? ? ? ? ? ? ? ? 0x17 (0x37) osicsr ? ? ? osisel0 ? ? osist osien 33 0x16 (0x36) tifr1 ? ? ? ? icf1 ocf1b ocf1a tov1 96 0x15 (0x35) tifr0 ? ? ? ? icf0 ocf0b ocf0a tov0 96 0x14 (0x34) reserved ? ? ? ? ? ? ? ? 0x13 (0x33) reserved ? ? ? ? ? ? ? ? 0x12 (0x32) reserved ? ? ? ? ? ? ? ? 0x11 (0x31) reserved ? ? ? ? ? ? ? ? 0x10 (0x30) reserved ? ? ? ? ? ? ? ? 0x0f (0x2f) reserved ? ? ? ? ? ? ? ? 0x0e (0x2e) reserved ? ? ? ? ? ? ? ? 0x0d (0x2d) reserved ? ? ? ? ? ? ? ? 0x0c (0x2c) reserved ? ? ? ? ? ? ? ? 0x0b (0x2b) reserved ? ? ? ? ? ? ? ? 0x0a (0x2a) reserved ? ? ? ? ? ? ? ? 0x09 (0x29) reserved ? ? ? ? ? ? ? ? 0x08 (0x28) portc ? ? portc5 portc4 portc3 portc2 portc1 portc0 66 0x07 (0x27) reserved ? ? ? ? ? ? ? ? 0x06 (0x26) pinc ? ? ? pinc4 pinc3 pinc2 pinc1 pinc0 66 0x05 (0x25) portb portb7 portb6 portb 5 portb4 portb3 portb2 portb1 portb0 78 0x04 (0x24) ddrb ddb7 ddb6 ddb 5 ddb4 ddb3 ddb2 ddb1 ddb0 78 0x03 (0x23) pinb pinb7 pinb6 pinb5 pinb4 pinb3 pinb2 pinb1 pinb0 78 0x02 (0x22) porta ? ? ? ? porta3 porta2 porta1 porta0 78 0x01 (0x21) ddra ? ? ? ? dda3 dda2 dda1 dda0 78 0x00 (0x20) pina ? ? ? ? pina3 pina2 pina1 pina0 78 address name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 page
13 8042b?avr?06/10 atmega16hvb/32hvb 8. instruction set summary mnemonics operands description operation flags #clocks arithmetic and logic instructions add rd, rr add two registers rd rd + rr z,c,n,v,h 1 adc rd, rr add with carry two registers rd rd + rr + c z,c,n,v,h 1 adiw rdl,k add immediate to word rdh:rdl rdh:rdl + k z,c,n,v,s 2 sub rd, rr subtract two registers rd rd - rr z,c,n,v,h 1 subi rd, k subtract constant from register rd rd - k z,c,n,v,h 1 sbc rd, rr subtract with carry two registers rd rd - rr - c z,c,n,v,h 1 sbci rd, k subtract with carry constant from reg. rd rd - k - c z,c,n,v,h 1 sbiw rdl,k subtract immediate from word rdh:rdl rdh:rdl - k z,c,n,v,s 2 and rd, rr logical and registers rd rd ? rr z,n,v 1 andi rd, k logical and register and constant rd rd ? k z,n,v 1 or rd, rr logical or registers rd rd v rr z,n,v 1 ori rd, k logical or register and constant rd rd v k z,n,v 1 eor rd, rr exclusive or registers rd rd rr z,n,v 1 com rd one?s complement rd 0xff ? rd z,c,n,v 1 neg rd two?s complement rd 0x00 ? rd z,c,n,v,h 1 sbr rd,k set bit(s) in register rd rd v k z,n,v 1 cbr rd,k clear bit(s) in register rd rd ? (0xff - k) z,n,v 1 inc rd increment rd rd + 1 z,n,v 1 dec rd decrement rd rd ? 1 z,n,v 1 tst rd test for zero or minus rd rd ? rd z,n,v 1 clr rd clear register rd rd rd z,n,v 1 ser rd set register rd 0xff none 1 mul rd, rr multiply unsigned r1:r0 rd x rr z,c 2 muls rd, rr multiply signed r1:r0 rd x rr z,c 2 mulsu rd, rr multiply signed with unsigned r1:r0 rd x rr z,c 2 fmul rd, rr fractional multiply unsigned r1:r0 (rd x rr) << 1 z,c 2 fmuls rd, rr fractional multiply signed r1:r0 (rd x rr) << 1 z,c 2 fmulsu rd, rr fractional multiply signed with unsigned r1:r0 (rd x rr) << 1 z,c 2 branch instructions rjmp k relative jump pc pc + k + 1 none 2 ijmp indirect jump to (z) pc z none 2 jmp k direct jump pc knone3 rcall k relative subroutine call pc pc + k + 1 none 3 icall indirect call to (z) pc znone3 call k direct subroutine call pc knone4 ret subroutine return pc stack none 4 reti interrupt return pc stack i 4 cpse rd,rr compare, skip if equal if (rd = rr) pc pc + 2 or 3 none 1/2/3 cp rd,rr compare rd ? rr z, n,v,c,h 1 cpc rd,rr compare with carry rd ? rr ? c z, n,v,c,h 1 cpi rd,k compare register with immediate rd ? k z, n,v,c,h 1 sbrc rr, b skip if bit in register cleared if (rr(b)=0) pc pc + 2 or 3 none 1/2/3 sbrs rr, b skip if bit in register is set if (rr(b)=1) pc pc + 2 or 3 none 1/2/3 sbic p, b skip if bit in i/o register cleared if (p(b)=0) pc pc + 2 or 3 none 1/2/3 sbis p, b skip if bit in i/o register is set if (p(b)=1) pc pc + 2 or 3 none 1/2/3 brbs s, k branch if status flag set if (sreg(s) = 1) then pc pc+k + 1 none 1/2 brbc s, k branch if status flag cleared if (sreg(s) = 0) then pc pc+k + 1 none 1/2 breq k branch if equal if (z = 1) then pc pc + k + 1 none 1/2 brne k branch if not equal if (z = 0) then pc pc + k + 1 none 1/2 brcs k branch if carry set if (c = 1) then pc pc + k + 1 none 1/2 brcc k branch if carry cleared if (c = 0) then pc pc + k + 1 none 1/2 brsh k branch if same or higher if (c = 0) then pc pc + k + 1 none 1/2 brlo k branch if lower if (c = 1) then pc pc + k + 1 none 1/2 brmi k branch if minus if (n = 1) then pc pc + k + 1 none 1/2 brpl k branch if plus if (n = 0) then pc pc + k + 1 none 1/2 brge k branch if greater or equal, signed if (n v= 0) then pc pc + k + 1 none 1/2 brlt k branch if less than zero, signed if (n v= 1) then pc pc + k + 1 none 1/2 brhs k branch if half carry flag set if (h = 1) then pc pc + k + 1 none 1/2 brhc k branch if half carry flag cleared if (h = 0) then pc pc + k + 1 none 1/2 brts k branch if t flag set if (t = 1) then pc pc + k + 1 none 1/2 brtc k branch if t flag cleared if (t = 0) then pc pc + k + 1 none 1/2 brvs k branch if overflow flag is set if (v = 1) then pc pc + k + 1 none 1/2 brvc k branch if overflow flag is cleared if (v = 0) then pc pc + k + 1 none 1/2
14 8042b?avr?06/10 atmega16hvb/32hvb brie k branch if interrupt enabled if ( i = 1) then pc pc + k + 1 none 1/2 brid k branch if interrupt disabled if ( i = 0) then pc pc + k + 1 none 1/2 bit and bit-test instructions sbi p,b set bit in i/o register i/o(p,b) 1none2 cbi p,b clear bit in i/o register i/o(p,b) 0none2 lsl rd logical shift left rd(n+1) rd(n), rd(0) 0 z,c,n,v 1 lsr rd logical shift right rd(n) rd(n+1), rd(7) 0 z,c,n,v 1 rol rd rotate left through carry rd(0) c,rd(n+1) rd(n),c rd(7) z,c,n,v 1 ror rd rotate right through carry rd(7) c,rd(n) rd(n+1),c rd(0) z,c,n,v 1 asr rd arithmetic shift right rd(n) rd(n+1), n=0..6 z,c,n,v 1 swap rd swap nibbles rd(3..0) rd(7..4),rd(7..4) rd(3..0) none 1 bset s flag set sreg(s) 1 sreg(s) 1 bclr s flag clear sreg(s) 0 sreg(s) 1 bst rr, b bit store from register to t t rr(b) t 1 bld rd, b bit load from t to register rd(b) tnone1 sec set carry c 1c1 clc clear carry c 0 c 1 sen set negative flag n 1n1 cln clear negative flag n 0 n 1 sez set zero flag z 1z1 clz clear ze ro flag z 0 z 1 sei global interrupt enable i 1i1 cli global interrupt disable i 0 i 1 ses set signed test flag s 1s1 cls clear signed test flag s 0 s 1 sev set twos complement overflow. v 1v1 clv clear twos complement overflow v 0 v 1 set set t in sreg t 1t1 clt clear t in sreg t 0 t 1 seh set half carry flag in sreg h 1h1 clh clear half carry flag in sreg h 0 h 1 data transfer instructions mov rd, rr move between registers rd rr none 1 movw rd, rr copy register word rd+1:rd rr+1:rr none 1 ldi rd, k load immediate rd knone1 ld rd, x load indirect rd (x) none 2 ld rd, x+ load indirect and post-inc. rd (x), x x + 1 none 2 ld rd, - x load indirect and pre-dec. x x - 1, rd (x) none 2 ld rd, y load indirect rd (y) none 2 ld rd, y+ load indirect and post-inc. rd (y), y y + 1 none 2 ld rd, - y load indirect and pre-dec. y y - 1, rd (y) none 2 ldd rd,y+q load indirect with displacement rd (y + q) none 2 ld rd, z load indirect rd (z) none 2 ld rd, z+ load indirect and post-inc. rd (z), z z+1 none 2 ld rd, -z load indirect and pre-dec. z z - 1, rd (z) none 2 ldd rd, z+q load indirect with displacement rd (z + q) none 2 lds rd, k load direct from sram rd (k) none 2 st x, rr store indirect (x) rr none 2 st x+, rr store indirect and post-inc. (x) rr, x x + 1 none 2 st - x, rr store indirect and pre-dec. x x - 1, (x) rr none 2 st y, rr store indirect (y) rr none 2 st y+, rr store indirect and post-inc. (y) rr, y y + 1 none 2 st - y, rr store indirect and pre-dec. y y - 1, (y) rr none 2 std y+q,rr store indirect with displacement (y + q) rr none 2 st z, rr store indirect (z) rr none 2 st z+, rr store indirect and post-inc. (z) rr, z z + 1 none 2 st -z, rr store indirect and pre-dec. z z - 1, (z) rr none 2 std z+q,rr store indirect with displacement (z + q) rr none 2 sts k, rr store direct to sram (k) rr none 2 lpm load program memory r0 (z) none 3 lpm rd, z load program memory rd (z) none 3 lpm rd, z+ load program memory and post-inc rd (z), z z+1 none 3 spm store program memory (z) r1:r0 none - in rd, p in port rd pnone1 8. instruction set summary (continued) mnemonics operands description operation flags #clocks
15 8042b?avr?06/10 atmega16hvb/32hvb out p, rr out port p rr none 1 push rr push register on stack stack rr none 2 pop rd pop register from stack rd stack none 2 mcu control instructions nop no operation none 1 sleep sleep (see specific descr. for sleep function) none 1 wdr watchdog reset (see specific descr. for wdr/timer) none 1 break break for on-chip debug only none n/a 8. instruction set summary (continued) mnemonics operands description operation flags #clocks
16 8042b?avr?06/10 atmega16hvb/32hvb 9. ordering information 9.1 atmega16hvb speed (mhz) power supply ordering code package operation range 1 - 8 mhz 4 - 25v atmega16hvb-8x3 44x1 -40 c to 85 c package type 44x1 44-lead, 4.4 mm body width, plastic th in shrink small outline package (tssop)
17 8042b?avr?06/10 atmega16hvb/32hvb 9.2 atmega32hvb speed (mhz) power supply ordering code package operation range 1 - 8 mhz 4 - 25v ATMEGA32HVB-8X3 44x1 -40 c to 85 c package type 44x1 44-lead, 4.4 mm body width, plastic th in shrink small outline package (tssop)
18 8042b?avr?06/10 atmega16hvb/32hvb 10. packaging information 10.1 44x1 title drawing no. r rev. n ote: these dra w ings are for general information only. refer to jedec dra w ing mo-153be. 2325 orchard park w ay san jose, ca 95131 5/16/07 44x1 , 44-lead, 4.4 mm body w idth, plastic thin shrink small o u tline package (tssop) 44x1 a common dimen s ion s (unit of meas u re = mm) s ymbol min nom max note a ?? 1.20 a1 0.05 ? b 0.17 ? 0.27 c 0.09 ? 0.20 d 10.90 11.00 11.10 e1 4.30 4.40 4.50 e 6.20 6.40 6.60 e 0.50 typ l 0.50 0.60 0.70 ? 0 o ? 8 o s ide view top view end view ? 1 44 2 3 l c e1 e d e b a a1 0.15 title drawing no. r rev. n ote: these dra w ings are for general information only. refer to jedec dra w ing mo-153be. 2325 orchard park w ay san jose, ca 95131 5/16/07 44x1 , 44-lead, 4.4 mm body w idth, plastic thin shrink small o u tline package (tssop) 44x1 a common dimen s ion s (unit of meas u re = mm) s ymbol min nom max note a ?? 1.20 a1 0.05 ? 0.15 b 0.17 ? 0.27 c 0.09 ? 0.20 d 10.90 11.00 11.10 e1 4.30 4.40 4.50 e 6.20 6.40 6.60 e 0.50 typ l 0.50 0.60 0.70 ? 0 o ? 8 o s ide view top view end view ? 1 44 2 3 l c e1 e d e b a a1
19 8042b?avr?06/10 atmega16hvb/32hvb 11. errata 11.1 atmega16hvb 11.1.1 rev. a no known errata. 11.2 atmega32hvb 11.2.1 rev. a no known errata.
20 8042b?avr?06/10 atmega16hvb/32hvb 12. revision history please note that the referring page numbers in this section are referring to this document. the referring revision in this section are referring to the document revision. 12.1 rev. 8042b?06/10 12.2 rev. 8042a?08/09 1. removed direction arrow in figure 17-1 on page 82 . updated ?configuring pa1 and pa0 for v-adc operation? on page 118 . updated ?operating circuit? on page 225 , with correct naming convention for thermistors rt32 and rt33. 1. initial revision
8042b?avr?06/10 headquarters international atmel corporation 2325 orchard parkway san jose, ca 95131 usa tel: 1(408) 441-0311 fax: 1(408) 487-2600 atmel asia unit 1-5 & 16, 19/f bea tower, millennium city 5 418 kwun tong road kwun tong, kowloon hong kong tel: (852) 2245-6100 fax: (852) 2722-1369 atmel europe le krebs 8, rue jean-pierre timbaud bp 309 78054 saint-quentin-en- yvelines cedex france tel: (33) 1-30-60-70-00 fax: (33) 1-30-60-71-11 atmel japan 9f, tonetsu shinkawa bldg. 1-24-8 shinkawa chuo-ku, tokyo 104-0033 japan tel: (81) 3-3523-3551 fax: (81) 3-3523-7581 product contact web site www.atmel.com technical support avr@atmel.com sales contact www.atmel.com/contacts literature requests www.atmel.com/literature disclaimer: the information in this document is provided in connection with atmel products. no license, express or implied, by estoppel or otherwise, to any intellectual property right is granted by this document or in connection with the sale of atmel products. except as set forth in atmel?s terms and condi- tions of sale located on atmel?s web site, atmel assumes no li ability whatsoever and disclaims any express, implied or statutor y warranty relating to its products including, but not limited to, the implied warranty of merchantability, fitness for a particu lar purpose, or non-infringement. in no event shall atmel be liable for any direct, indirect, consequential, punitive, special or i nciden- tal damages (including, without limitation, damages for loss of profits, business interruption, or loss of information) arising out of the use or inability to use this document, even if atme l has been advised of the possibility of such damages. atmel makes no representations or warranties with respect to the accuracy or comp leteness of the contents of this document and reserves the rig ht to make changes to specifications and product descriptions at any time without notice. atmel does not make any commitment to update the information contained her ein. unless specifically provided otherwise, atmel products are not suitable for, and shall not be used in, automotive applications. atmel?s products are not int ended, authorized, or warranted for use as components in applications in tended to support or sustain life. ? 2010 atmel corporation. all rights reserved. atmel ? , atmel logo and combinations thereof, avr ? , avr ? logo and others are registered trade- marks or trademarks of atmel corporation or its subsidiari es. other terms and product names may be trademarks of others.

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